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[Other] u26a_spice

Description: ddr2控制器一些源码，控制时序及怎样通过嵌入式cpu来进行控制的实例-ddr2 Controller some source code, and how to control the timing of embedded cpu passed to the control of the examples
Platform: | Size: 297984 | Author: | Hits:

[VHDL-FPGA-Verilog] xapp935

Description: ddr2 controller, verilog source code from xilinx
Platform: | Size: 347136 | Author: Hubert | Hits:

[Compress-Decompress algrithms] DDR2_sdram

Description: DDR2 的控制器，它是由LATTICE的编译器生成。-DDR2 controller, it is by the compiler-generated LATTICE.
Platform: | Size: 966656 | Author: 李国 | Hits:

[VHDL-FPGA-Verilog] zbt_rd_vhdl_str_v1.0.0

Description: ddr2 controller功能控制,里面有四个模块-ddr2 controller functions to control, which has four modules
Platform: | Size: 1688576 | Author: li ji wei | Hits:

[VHDL-FPGA-Verilog] vga_control

Description: vga 控制器的verilog 源码 ，fpga上可实现图片的显示-vga controller Verilog source code, fpga achievable picture display
Platform: | Size: 1024 | Author: zys | Hits:

[VHDL-FPGA-Verilog] DDR2Controller

Description: DDR2 Controller DDR2 Controller
Platform: | Size: 312320 | Author: tg | Hits:

[VHDL-FPGA-Verilog] OpenSPARC_DDR2_controller_RTL_Files

Description: 基于FPGA的DDR2控制程序，用verilog编写的。-FPGA-based DDR2 control procedures, prepared by using Verilog.
Platform: | Size: 30720 | Author: 王头 | Hits:

[VHDL-FPGA-Verilog] Micron_SDRAM_DDR2Simulation_model_Verilog

Description: DDR2 SDRAM仿真模型，适合于ModelSim下工作，请先阅读readme-DDR2 SDRAM Simulation Model which is suitable for modelsim. Please read readme file firstly.
Platform: | Size: 20480 | Author: rar | Hits:

[VHDL-FPGA-Verilog] Xil3SD1800A_MIG_simplifiedUI_vlog_v92

Description: verilog 实现的spartan 3A dsp start kit DDR2 SDRAM 控制器-verilog achieved spartan 3A dsp start kit DDR2 SDRAM controller
Platform: | Size: 908288 | Author: ma yirong | Hits:

[VHDL-FPGA-Verilog] ddr2

Description: 基于Xilinx fpga的ddr2 控制器设计方法-Xilinx fpga-based controller design method of ddr2
Platform: | Size: 2793472 | Author: Zhao Bill | Hits:

[VHDL-FPGA-Verilog] DDR2_controller

Description: DDR2控制器IP的设计与FPGA实现，使用verilog语言-DDR2 Controller IP Design and FPGA implementation, use the verilog language
Platform: | Size: 1818624 | Author: alins | Hits:

[VHDL-FPGA-Verilog] ssss

Description: spartan—3a对ddr2读写控制源程序，有verilog和vhdl版本-spartan-3a ddr2 read and write control of the source, there are versions of verilog and vhdl
Platform: | Size: 324608 | Author: 刘一平 | Hits:

[VHDL-FPGA-Verilog] NET2

Description: This file with the wavelet transf Mallat implementation of wavelet Verilog hdl code modules for radi Modelsim 6.6 crack, can be used f A written using Verilog DDR2 cont Simple CPU VHDL implementation an Dual-port RAM design, using Veril Verilog language, a hardware-base FPGA embedded project combat, Man Application FPGA, FPGA-chip hardw Mallat implementation of wavelet Layer of one-dimensional wavelet
Platform: | Size: 1852416 | Author: sansfroid | Hits:

[VHDL-FPGA-Verilog] DDR2_Memory_Test

Description: DDR2 controller which contains verilog files，pdf and so on
Platform: | Size: 234496 | Author: zhang | Hits:

[VHDL-FPGA-Verilog] ddr

Description: 利用硬件verilog语言实现DDR2功能，对信息快速存储-VERILOG DDR2
Platform: | Size: 316416 | Author: | Hits:

[VHDL-FPGA-Verilog] DDRCHv11

Description: Source code for ddr2 dram controller for BEEE
Platform: | Size: 661504 | Author: shiva | Hits:

[VHDL-FPGA-Verilog] DDR2-verilog

Description: Verilog程序设计实例中，DDR部分的程序代码-Verilog programming example, DDR part of the program code
Platform: | Size: 1221632 | Author: 林传正 | Hits:

[VHDL-FPGA-Verilog] DDR2-verilog

Description: ddr2的Verilog代码，包括时序控制，数据读取，利用verilog编写的ddr2控制器，在spartan6板子上得以验证，成功实现了FPGA与DDR2的通信。-ddr2 of Verilog code, including timing control, data is read using verilog prepared ddr2 controller board on spartan6 be verified, the successful implementation of the FPGA and DDR2 communications.
Platform: | Size: 1490944 | Author: wei | Hits:

[VHDL-FPGA-Verilog] ddr2_module

Description: 设计的DDR2的verilog代码.改代码实现读取DDR2的数据。(the code for DDR2.It is used for reading the data of DDR2)
Platform: | Size: 3072 | Author: fuyhfut | Hits:

[VHDL-FPGA-Verilog] DDR2_Control

Description: 参考例程之Verilog之实现DDR2时序控制实现，ISE开发平台完整工程(Implementation of DDR2 timing control implementation of reference routine Verilog, complete engineering of ISE development platform)
Platform: | Size: 13038592 | Author: tomll | Hits:
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